Field of the Invention
The present invention relates to a vertical transistor that has a lower doping region, an upper doping region, and a channel, and to a method for its fabrication.
Vertical transistors are field-effect transistors in which the source region and drain region are disposed one above the other, rather than next to one another in a single plane, as is the case in planar field-effect transistors.
By way of example, U.S. Pat. No. 5,177,576 to Kimura et al. describes vertical transistors that have a floating body effect. The floating body effect means that there is no contact with the channel region of the transistor, which is, therefore, electrically floating.
The floating body effect is also relevant to planar transistors. For example, it occurs in what are referred to as silicon on insulator (SOI) transistors, in which the channel region is enclosed between source region, drain region, lateral insulations, and SOI insulation so that it is not in contact with a substrate.
In non-SOI transistors, the contact with a substrate allows charges that are formed in the channel region to migrate into the substrate so that the channel is not subject to any electrical charging effects. By contrast, in SOI transistors the channel is insulated, which, for example in the event of capacitive crosstalk between adjacent structures, correspondingly leads to charging effects in the channel because the charges that are formed can no longer be removed. The charging effects in the channel lead to a control effect on the channel that is similar to the gate electrode. This control effect means that the transistor can no longer be switched on and off in a defined way. A transistor that can no longer be controlled loses its functionality and is, therefore, unusable.
It is accordingly an object of the invention to provide a vertical transistor and a corresponding fabrication method that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that avoids the floating body effect.
With the foregoing and other objects in view, in a substrate, there is provided, in accordance with the invention, a vertical transistor including a lower doping region disposed in the substrate, an upper doping region disposed in the substrate above the lower doping region, a channel region disposed between the lower doping region and the upper doping region, the substrate defining an isolation trench extending at least to the channel region, insulating material filling the isolation trench, a lower insulation filling in the isolation trench, an upper insulation filling in the isolation trench above the lower insulation filling, and a conductive layer disposed between the lower insulation filling and the upper insulation filling in the isolation trench.
A vertical transistor is usually isolated with the aid of an isolation trench. The isolation is carried out, for example, in a memory having a memory cell array in which adjacent memory cells, which include a trench capacitor and a vertical transistor as a select transistor, are isolated from one another. To save space, the individual memory cells of the memory cell array are disposed so close together that the channel region of the vertical transistor is completely insulated between the gate oxide, the isolation trench, and the doping regions. According to the invention, in such a memory cell configuration it is also possible for the isolation trench to be configured with a conductive layer that is disposed between an upper insulation filling and a lower insulation filling so that the channel region of the vertical transistor is connected to the substrate.
In accordance with another feature of the invention, the conductive layer makes electrical contact with the channel region. This ensures that an electrical contact prevents the channel region from becoming charged.
In accordance with a further feature of the invention, the upper insulation filling reaches the upper doping region. Such a configuration allows a space-saving layout that, additionally, has the advantage that the upper doping region is very well insulated from the substrate and an adjacent circuit. As a result, leakage currents are reduced.
Furthermore, in accordance with an added feature of the invention, it is advantageous for the lower insulation filling to reach the lower doping region. Such a configuration means that the depth of the isolation trench in the substrate is such that the lower doping region is also as far as possible insulated from the substrate, and, in this case too, leakage currents to adjacent parts of the circuit are avoided.
Furthermore, in accordance with an additional feature of the invention, it is advantageous for the conductive layer to be formed from silicon, doped silicon, polycrystalline silicon, amorphous silicon, tungsten nitride, titanium nitride, tantalum nitride, or a silicide. An important factor in the case of the silicon-containing materials is the good comparability with the channel region, which is usually formed from silicon. The doping of the silicon is selected such that a good electrical connection is ensured. Selecting one of the above mentioned nitrides has the advantage that they act as a barrier and, thus, prevent undesirable diffusion of materials. Furthermore, the above-mentioned nitrides have the advantage of having a good conductivity. Silicides can also be used, on account of their good conductivity.
In accordance with yet another feature of the invention, the lower insulation filling and the upper insulation filling are formed at least in part from silicon oxide, silicon nitride, and/or silicon oxynitride. The use of these materials ensures that the upper and lower doping regions have good insulation properties with respect to adjacent conductive structures.
With the objects of the invention in view, in a substrate, there is also provided a vertical transistor including a lower doping region disposed in the substrate, an upper doping region disposed in the substrate above the lower doping region, a channel region disposed between the lower doping region and the upper doping region, the substrate defining an isolation trench extending at least to the channel region, insulating material filling the isolation trench, the insulating material having a lower insulation filling and an upper insulation filling disposed above the lower insulation filling, and a conductive layer disposed between the lower insulation filling and the upper insulation filling in the isolation trench.
With the objects of the invention in view, there is also provided a vertical transistor including a substrate defining an isolation trench, a lower doping region in the substrate, an upper doping region in the substrate above the lower doping region, a channel region disposed between the lower doping region and the upper doping region, the isolation trench extending at least to the channel region, insulating material filling the isolation trench, the insulating material having a lower insulation filling and an upper insulation filling disposed above the lower insulation filling, and a conductive layer disposed between the lower insulation filling and the upper insulation filling in the isolation trench.
With the objects of the invention in view, there is also provided a method for fabricating a vertical transistor, including the steps of forming a lower doping region in a substrate, forming an upper doping region in the substrate above the lower doping region with a channel region being formed between the lower doping region and the upper doping region, forming an isolation trench at least next to the channel region, forming a lower insulation filling in the isolation trench, forming a conductive layer in the isolation trench on the lower insulation filling, and forming an upper insulation filling in the isolation trench on the conductive layer.
The layered fabrication of the filling of the isolation trench is advantageous because, in such a procedure, the conductive layer is formed at a suitable position in the isolation trench and adjoins the channel region. A further advantage is that there is no need for any lithography steps for fabrication of the filling of the isolation trench because the layer depositions used to form the insulation fillings and the conductive layer can be carried out as processes that cover the entire surface.
In accordance with yet a further mode of the invention, the conductive layer is formed such that it is electrically connected to the channel region. This has the advantage that charging effects of the channel region are avoided as a result of charges being removed through the conductive layer.
In accordance with yet an added mode of the invention, the lower insulation filling is formed such that the isolation trench is initially filled with an insulating material, which is, then, planarized at the substrate surface and is recessed into the isolation trench by an etchback step. This method step has the advantage that it can be carried out using conventional methods for the fabrication of isolation trench fillings. In addition, however, a recessing process is carried out, advantageously, down to a depth that uncovers the channel region.
In accordance with a concomitant mode of the invention, the conductive layer is applied to the lower insulation filling by a sputtering process. This process allows selective formation of the conductive layer on the lower insulation filling. In addition, the degree of base coverage is increased by what are referred to as back-sputtering processes so that the material that has been sputtered on can be removed from the side walls of the isolation trench using an etching process and a conductive layer is retained on the base of the isolation trench.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a vertical transistor and a corresponding fabrication method, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.